(1) Field of the Invention
The present invention relates to an adjustable attenuator circuit, more particularly to an adjustable attenuator circuit which comprises switched capacitors and which is used, for example, in an electronic circuit, such as a PCM coder or decoder.
(2) Description of the Prior Art
In a conventional adjustable attenuator circuit, the attenuation factor thereof is adjusted by inserting or bypassing each of the fixed attenuators having various attenuation factors. For example, as illustrated in FIG. 1, such an attenuator circuit comprises fixed attenuators AT1, AT2, AT3, AT4 and AT5 whose attenuation factors are 0.5 dB, 1.0 dB, 2.0 dB, 4.0 dB and 8.0 dB, respectively, and which are connected in cascade through electronic switches SW1 through SW10 and can be bypassed by each of the electronic switches SW11 through SW15. In the adjustable attenuator circuit of FIG. 1, it is possible to obtain the attenuation from 0 dB to 15.5 dB in a 0.5 dB step by the selective operation of the electronic switches SW1 through SW15.
However, in the above-mentioned conventional attenuator circuit, since the on-resistance and the off-resistance of each of the electronic switches affect the attenuation of the attenuator circuit, it is impossible to obtain a high precision attenuation factor. Especially when the adjustable attenuator circuit of FIG. 1 is formed in an integrated circuit, the error of the attenuation factor becomes large because the resistor characteristic of each of the electronic switches cannot be ideal due to the limitation of, for example, the space available to form the electronic switches.
There is known another conventional adjustable attenuator in which the attenuation factor thereof is determined by the ratio of the capacitances of the capacitors and which is disclosed, for example, in the thesis by G. L. Baldwin et al, "A CMOS Digitally-Control Analog Attenuator for Voice Band Signals", Proc. ISCAS '77, pp. 519-524. The attenuator circuit disclosed in this thesis comprises, as illustrated in FIG. 2, input capacitors having capacitances of C, C, 2C, 2.sup.2 C, . . . , 2.sup.K-1 C respectively, a feedback capacitor having a capacitance of 2.sup.K-1 C, a switch unit SW23 which comprises a plurality of switches, switches SW21 and SW22, and, an operational amplifier OP. The switches SW21 and SW22 are both operated at a sampling frequency higher than twice that of the highest frequency of an input signal V.sub.in. The attenuation factor of the attenuator circuit of FIG. 2 is determined by the positions of the switches of the switch unit SW23. The relation between the input signal V.sub.in and the output signal V.sub.out becomes as follows. EQU V.sub.out /V.sub.in =NC/(C.sub.T -NC) (1)
Where, N=1, 2, 3, . . . , 2.sup.K-1, C.sub.T =2.sup.K C, K+1 is a number of the input capacitors Ci, and, NC is the total capacitance of the input capacitors which are connected between the switch SW22 and the inverting input terminal of the operational amplifier OP via the switches of the switch unit SW23. Therefore, C.sub.T -NC is equal to the total capacitance of the input capacitors, which are connected between the inverting input terminal and the output terminal OUT of the operational amplifier OP. Since the details of the attenuator circuit of FIG. 2 are disclosed in the above-mentioned thesis, the detailed explanation thereof is omitted here.
However, it should be noted that, in the above-mentioned conventional attenuator circuit, it is necessary to set K to approximately 9 in order to obtain 32 steps of attenuation with precision. Practically, speaking in this case, the number of the steps of attenuation can be 2.sup.9-1 =256, and 32 steps of the 256 steps are utilized. The ratio of the maximum capacitance to the minimum capacitance of the input capacitors becomes 2.sup.8 and if the maximum capacitance of an input capacitor is 32pF, the minimum capacitance of an input capacitor is 0.125pF. Therefore, it is very difficult to form the capacitors having a large capacitance ratio and including the capacitors of very small capacitances with high precision in an integrated circuit.